In recent years, as semiconductor units have become more and more multifunctional, an increasing number of semiconductor units have multiple power supply systems within a single semiconductor unit where multiple circuits are divided and disposed so that each circuit is connected to a respective power supply system. Multiple power supply systems are provided when: (1) a single semiconductor unit uses multiple power supply voltages; (2) both analog circuits and digital circuits are used, and noisy digital power supply and ground (GND) need to be separated from analog power supply and ground (GND); (3) a temporarily unused circuit is turned off in order to save energy, and the power supply for this circuit needs to be separated from the power supply for circuits used all the time.
Next, such a semiconductor unit, where circuits belonging to multiple power supply systems are interconnected, will be described. FIG. 12 is a circuit block diagram of a conventional semiconductor unit where signals are sent/received between circuits belonging to different power supply systems (refer to Patent Document 1). In FIG. 12, a first circuit connected to a first power supply system comprises a power supply terminal V11 and a ground terminal G11, and a second circuit connected to a second power supply system comprises a power supply terminal V12 and a ground terminal G12. The ground terminal G11 and the ground terminal G12 are connected via a protection element PE10. Further, an ESD protection element PE11 is connected between the power supply terminal V11 and the ground terminal G11, and an ESD protection element PE12 is connected between the power supply terminal V12 and the ground terminal G12. The first circuit comprises subordinately connected PMOS transistor MP11 and NMOS transistor MN11. Further, the second circuit comprises subordinately connected PMOS transistor MP12 and NMOS transistor MN12.
During normal operation, the PMOS transistor MP11 and the NMOS transistor MN11 included in the first circuit send a signal to the PMOS transistor MP12 and the NMOS transistor MN12 included in the second circuit. In other words, the drains of the PMOS transistor MP11 and the NMOS transistor MN11 are common and connected to the interconnected gates of the PMOS transistor MP12 and the NMOS transistor MN1.
When ESD is applied, such as during an ESD test, assuming that the ground terminal G12 is grounded and a positive electric charge is applied to the power supply terminal V11, first, the electric charge injected into the power supply terminal V11 by ESD application is discharged to ground wiring GND11 connected to the ground terminal G11 primarily through the ESD protection element PE11, and it is then discharged to ground wiring GND12 via the ground wiring GND11 (a path P11.) In this case, it is ideally preferable that a resistance component parasitic on the connection between power supply wiring VDD11 and the ground wiring GND11, and between the ground wiring GND11 and the ground wiring GND12 be as close to zero as possible, and that a voltage drop that occurs when a current flows by applying ESD be almost zero. However, in reality, since the parasitic resistances of the ESD protection element, the power supply wiring VDD11, the ground wiring GND11, and the ground wiring GND12 exist, the potential of the power supply wiring VDD11 increases as the current flows by applying ESD. Moreover, since long distance wiring is provided, and in some cases, the protection element PE10 and a resistance element are inserted between the ground wiring GND11 and the ground wiring GND12, there are parasitic resistance components of the wiring and the inserted elements in the path where the current flows from the ground wiring GND11 to the ground wiring GND12. Therefore, the potential of the power supply wiring VDD11 is more likely to increase compared to the cases where electricity is discharged from the power supply wiring VDD11 to the ground wiring GND11 or from the power supply wiring VDD11 to the ground wiring GND12.
Meanwhile, when ESD is being applied, everything is floating except for the application pin and ground pin. When ESD is applied to the power supply terminal V11, the potentials of the gate electrodes of the PMOS transistor MP11 and NMOS transistor MN11 are floating, and the PMOS transistor MP11 is in an on state. In this state, the electric charge applied to the power supply terminal V11 is charged in the gate of the NMOS transistor MN12 through the PMOS transistor MP11 (a path P12). As mentioned before, the ground terminal G12 is grounded, therefore the maximum voltage amount that can be applied between the gate and the source/sub of the NMOS transistor MN12 is the voltage between the power supply wiring VDD11 and the ground wiring GND12.
As described above, since the current flows through multiple elements, the potential of the power supply wiring VDD11 increases and the voltage between the power supply wiring VDD11 and the ground wiring GND12 is directly applied to the gate oxide film of the NMOS transistor MN12. As a result, the NMOS transistor MN12 might get damaged. An operation where the ground terminal G12 is grounded and ESD is applied to the power supply terminal V11 was described here, however, when the power supply terminal V12 is grounded and ESD is applied to the power supply terminal V11, the PMOS transistor MP12 might get damaged in a similar operation. In the latest LSI manufacturing process, miniaturization and voltage reduction is advanced, and the breakdown voltage of the gate oxide films of the NMOS transistor MN12 and the PMOS transistor MP12 is getting lower and lower. Therefore, when ESD is applied between different power supply systems as described above, it is easy for the gate oxide film to be damaged by a low voltage.
As a measure to protect against such a damage, as shown in FIG. 13, an NMOS transistor MN13 as a gate protection element to protect the NMOS transistor MN12 and the PMOS transistor MP12 can be inserted (refer to Patent Document 2 for example). The NMOS transistor MN13 is turned off during normal operation and does not influence the signal transmission where the PMOS transistor MP11 and the NMOS transistor MN11 send a signal to the PMOS transistor MP12 and the NMOS transistor MN12. When ESD is applied, for instance, when the ground terminal G12 is grounded and ESD is applied to the power supply terminal V11, the electric charge of the ESD is charged in the gate of the NMOS transistor MN12 through the PMOS transistor MP11, and the NMOS transistor MN13 is turned on as soon as the gate potential of the NMOS transistor MN12 increases. Since the potential is limited so that the gate potential of the NMOS transistor MN12 will not surpass a predetermined value, the protection against ESD is improved, compared to the circuit shown in FIG. 12.
[Patent Document 1 ]    Japanese Patent Kokai Publication No. JP-A-9-172146 (FIG. 1)
[Patent Document 2 ]    Japanese Patent Kokai Publication No. JP-A-8-37238 (FIG. 7)